The invention relates to dynamic random access memories (DRAMs), and in particular, to the control of a read access and to the supervision of the operation of the read/rewrite amplifiers. The invention applies advantageously but not limitingly to embedded dynamic memories (embedded DPAMs), that is, memories which are made jointly with other components by the same process, for example, and are intended to be integrated together within an application specific integrated circuit (ASIC).
The information stored in a static random access memory (SRAM) remains so indefinitely, at least for as long as the memory remains energized. In contrast, a dynamic memory requires a periodic refreshing of the information stored on account of the stray leakage currents. In particular, the stray leakage currents discharge the storage capacitance of each memory slot.
Among the mentioned dynamic random access memory cells, they may be made, in particular, to comprise one, two or three transistors. Conventionally, dynamic random access memories are organized as rows and columns of memory cells. Each column comprises a metallization path commonly referred to as a bit line and an immediately adjacent bit line referred to as a reference or inverse bit line.
Precharging means are provided for each column for precharging the bit line and the reference bit line associated with a column before a read access of the memory is performed. Precharging the bit lines and the reference bit lines is generally performed at a voltage equal to Vdd/2 in the case where the supply voltage Vdd represents the storage voltage for a high state (typically a logic 1), and 0 volts (ground) represents the storage voltage for a low state (typically a logic 0).
Most DRAM devices use a row of reference cells, also connected to the bit lines and the reference bit lines, to equalize the charges applied thereto and to maximize the mean amplitude of the signal between the 0""s and the 1""s. Other precharging means are also provided for precharging a row of reference cells. The precharging of the reference cells is generally also performed at Vdd/2.
During a read access of a memory cell connected to a bit line, this cell and a reference cell connected to the reference bit line are selected (activated), then the sign of the difference in voltage between the bit line and the reference bit line is detected to determine the logic content of the memory cell, i.e., a logic 0 or 1.
These detections are conventionally performed with the aid of a read/rewrite amplifier connected between the bit line and the reference bit line. This amplifier generally comprises two looped-back inverters forming a bistable flip-flop. Each is formed of two complementary transistors and controlled by two successive signals. These two signals are read and rewrite, which are commonly known as sense and restore signals. Upon the activation of the restore signal, the data item read from the memory cell is rewritten, thus refreshing the content of this memory cell. However, a conventional memory structure of this kind has certain drawbacks.
Specifically, after precharging the bit line and the reference bit line of a column, and during the selection of the memory cell, the voltage at the gates of the two NMOS transistors of the read/rewrite amplifier is substantially on the order of Vdd/2. Upon activation of the sense signal, the source of these two NMOS transistors is then grounded. It follows from this that the gate-source voltage of these NMOS transistors is then substantially equal to Vdd/2. These transistors are on if the gate-source voltage is greater than the threshold voltage of these transistors.
Also, as the technology evolves, the level of the supply voltage is dropping, while the threshold voltage of an NMOS transistor remains substantially constant. Thus, for 0.18 micron technology, the supply voltage is on the order of 1.8 volts, while for 0.12 micron technology it is on the order of 1.2 volts.
Consequently, with advanced technologies and in particular the 0.15 micron and less technologies, the difference between the gate-source voltage of the NMOS transistor and its threshold voltage may become very small, even less than the threshold voltage or offset of the amplifier. This leads to erroneous rewriting and erroneous refreshing of the data item read. In the worst case, this voltage difference may be negative, thereby preventing the NMOS transistors of the amplifier from being turned on, and consequently, stopping it from operating.
In view of the foregoing background, an object of the present invention is to provide for the proper operation of the read/rewrite amplifier, and in particular for advanced technologies, such as 0.15 or 0.12 micron or less technologies.
The invention therefore provides a process for controlling a read access for a memory cell of a memory plane or memory array of a dynamic random access memory device. The memory cell is connected to a bit line of the memory plane and is associated with a read/rewrite amplifier connected between the bit line and a reference bit line. The control process comprises a phase of precharging the bit line and the reference bit line to a predetermined precharge voltage (e.g., Vdd/2), and a phase of reading and refreshing the content of the selected memory cell based upon an activated read/rewrite amplifier.
According to a general characteristic of the invention, between the precharging phase and the reading and refreshing phase, two capacitors previously charged to a charging voltage greater than the precharge voltage (for example, to a charging voltage equal to Vdd) are respectively connected to the bit line and to the reference bit line.
Stated otherwise, according to the invention, the common-mode voltage of the read/rewrite amplifier is thus increased before the reading and refreshing phase so as to increase the voltage on the gate of the NMOS transistors and consequently obtain a bigger gate-source voltage difference across the terminals of the NMOS transistors, even with a smaller supply voltage.
According to one mode of implementation of the invention, each capacitor is charged for a predetermined duration. For example, the duration is equal to the duration of precharging the bit lines and the reference bit lines. The charging is stopped just before connecting the capacitor thus charged to the corresponding bit line. By stopping the charging just before connecting the capacitor to the corresponding bit line, it is thus possible to minimize the stray leakages.
The invention also provides a dynamic random access memory device comprising a memory plane that includes columns each formed of a bit line and a reference bit line, to which are connected rows of memory cells. A read/rewrite controllable amplifier is preferably connected to each column of the memory plane, and controllable means select a row of memory cells. Controllable means of column precharging, connected to each column, precharge the bit line and the reference bit line of a column connected to a selected memory cell to a predetermined precharge voltage.
The dynamic random access memory device preferably further includes two capacitors respectively connected to the bit line and to the reference bit line of a column by two controllable connection interrupters. Controllable means of charging charges each capacitor to a charging voltage greater than the precharge voltage, and control means for activating the means of charging the capacitors and to activate in succession the precharging means, the two connection interrupters, the selection means and the read/rewrite amplifier is also provided for controlling the read access of the selected memory cell.
According to one embodiment of the invention, the control means are able to activate the charging means for a predetermined duration, then to deactivate the charging means just before closing the two connection interrupters. The charging means advantageously comprises, for each capacitor, a controllable charging interrupter connected between a voltage source delivering the charging voltage, e.g., the supply voltage, and a terminal of the capacitor.